This invention relates to phase-locked loop circuitry for programmable logic devices. More particularly, this invention relates to a phase-locked loop circuit for a programmable logic device having greater flexibility in adjusting both frequency and phase of the output signal relative to those of the input signal.
Programmable logic devices are well known. Commonly, a programmable logic device has a plurality of substantially identical logic elements, each of which can be programmed to perform certain desired logic functions. The logic elements have access to a programmable interconnect structure that allows a user to interconnect the various logic elements in almost any desired configuration. Finally, the interconnect structure also provides access to a plurality of input/output (“I/O”) pins, with the connections of the pins to the interconnect structure also being programmable.
At one time, programmable logic devices of the type just described were implemented almost exclusively using transistor—transistor logic (“TTL”), in which a logical “high” signal was nominally at 5 volts, while a logical “low” signal was nominally at ground potential, or 0 volts. More recently, however, other logic standards have come into general use, some of which use different signalling schemes, such as LVTTL (Low Voltage TTL), PCI (Peripheral Component Interface), SSTL (Series Stub Terminated Logic, which has several variants), GTL (Gunning Transceiver Logic) or GTL+, HSTL (High Speed Transceiver Logic, which has several variants), LVDS (Low Voltage Differential Signalling), and others. Some of these signalling schemes, and particularly LVDS, require high-frequency clock signals with precise phase relationships for proper operation.
It is known to include phase-locked loop circuitry on programmable logic devices to help counteract “skew” and excessive delay in clock signals propagating on the device (see, for example, Jefferson U.S. Pat. No. 5,699,020 and Reddy et al. U.S. Pat. No. 5,847,617, both of which are hereby incorporated by reference herein in their entireties). For example, phase-locked loop circuitry may be used to produce a clock signal which is advanced in time relative to a clock signal applied to the programmable logic device. The advanced clock signal is propagated to portions of the device that are relatively distant from the applied clock signal so that the propagation delay of the advanced clock signal brings it back into synchronism with the applied clock signal when it reaches the distant portions of the device. In this way all portions of the device receive synchronous clock signals and clock signal “skew” (different amounts of delay in different portions of the device) is reduced.
However, while phase-locked loops are accurate sources of clock signals, they generally are limited in the frequencies they can provide, both in terms of adjustability, and in terms of the absolute range of frequencies that can be generated. Moreover, the ability to adjust the phase of the output clock signal relative to the input clock signal is limited.
It would be desirable to be able to provide a phase-locked loop circuit that is adjustable in phase and can generate a wide range of frequencies.
It would be particularly desirable to be able to provide such a phase-locked loop circuit on a programmable logic device, especially to provide a clock signal for a high-speed signalling scheme, such as LVDS.